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Cobham Introduces Two New Open Source Processor IP Cores

By Rachel Jewett | December 12, 2019

Cobham introduces new LEON5 IP core. Photo: Cobham

Cobham Advanced Electronic Solutions
revealed Thursday that it has introduced two new offerings to its Cobham Gaisler family of Open Source IP Cores. The new LEON5 IP core implements the SPARC V8 32-bit Instruction Set Architecture (ISA), a 32-bit architecture. And Cobham’s new NOEL-V supports RISC-V, an open, free ISA that enables processor innovation through open standard collaboration. NOEL-V is Cobham’s initial RISC-V solution and the company plans to introduce a range of RISC-V offerings. 

Both of Cobham’s new Processor IP Cores will be available for initial download into Xilinx UltraSCALE FPGAs, and both processors will be fully integrated with Cobham’s GRLIB VHDL IP core library. 

“Cobham has a longstanding tradition of delivering open source solutions in order to expedite the development of next-generation computing devices for the space industry,” said Kevin Jackson, Cobham’s vice president and general manager, space and semiconductor solutions. “Our new LEON5 achieves a major improvement in terms of compute performance, while simultaneously allowing a smooth upgrade path and software re-use for our existing LEON user base.”